- Vhdl Program For Parallel In Serial Out Shift Register
- Parallel In Serial Out Block Diagram
- Shift Register
- Parallel In Serial Out Shift Register Vhdl
- Simple 3 to 8 bit decoder implementation in FPGA by VHDL and Verilog - Duration: 17:37. Khalid Nazmus Sakib. Parallel in serial out shift register - Duration: 7:26. Ajay chaudhary 10,431.
- Parallel-in/ serial-out shift registers do everything that the previous serial-in/ serial-out shift registers do plus input data to all stages simultaneously. The parallel-in/ serial-out shift register stores data, shifts it on a clock by clock basis, and delays it by the number of stages times the clock period.
- The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to parallel-out one above. The data is loaded into the register in a parallel format in which all the data bits enter their inputs simultaneously, to the parallel input pins P A to P D of the register.
VHDL Shift Register. Posted by Shannon Hilbert in Verilog / VHDL on 2-6-13. Shift registers are a fundamental part of nearly every FPGA design, allowing the ability to delay the flow of data and examine previous values in the architecture pipeline.
$begingroup$I'm creating an n bit shift register. When the enable signal is high, I want the shift register to shift n times, irrespective of whether enable continues to be high or low. I've put a for loop to shift n times inside a process. My code is given below.
I don't think the for loop is working, as the shifting is not restricted to n times. Where am I going wrong?
Federico Russo
2 Answers
$begingroup$In VHDL, a for loop executes in zero time. This means that instead of waiting a clock cycle between each iteration, the entire loop is run within one clock cycle, with only the final result of the loop being shown at the end. This is what's happening in your code. The entire loop is executing in a single clock cycle, and the value of s_out is only going to change once - to the value it was when the loop ended, which in this case is s_in shifted by 4.
What you really want is a loop where each iteration occurs on a new clock edge. This allows for s_in to be shifted out of s_out ever clock cycle.
Performing a loop where each iteration occurs on a clock edge does not require a for loop command, instead it takes advantage of the sensitivity list of the process. Here's how:
A process is triggered every time one of the signals on the sensitivity list ('clk, reset' in this case) changes. This means that the process is already looping every clock cycle (if a clock is in the sensitivity list). You can use this to your advantage in order to perform a for-loop type operation, where every iteration of the loop occurs on a clock cycle.
First you need a counter:
shift_counter keeps track of how many iterations (or shifts) have occurred so far. you'll compare shift_counter to n-1 to see if you're done yet.
Next it might be a good idea to think of the states your process will be in. Perhaps a wait state for when the process is not shifting, and a shifting state for when it is.
The state signal definition:
In the process proper:
Ok, so what happens when we're waiting for an enable? It would be a good idea to set all (driven) variables to a known value. This means that maybe something like this is a good idea:
This is useful to do because then you know exactly what your signal values are when enable goes high. Also, at the end of the shift, you can change states back to 'waiting' in order to get ready for enable again.
So what is going to trigger a state change from waiting to shifting ?That's easy:
Ok, so next state. shifting.
First, we want to increment the shift counter, and perform the actual shift:
And then also detect when the shifting is done, in order to leave the shift state and go back to waiting:
And that's it!
In the below chunk of code, note that the 'reset' state and the 'waiting' state are distinct. This is useful because generally the asynchronous reset only occurs at startup and is not expected to process any data during this time. By moving the temp_reg <= parallel_in to the waiting state (outside of the asynchronous reset), we are allowing the module driving parallel_in to start up correctly without having to send data during reset. Also, now the waiting state can be entered as necessary, without having to perform an asynchronous reset.
Also notice that I'm only driving 3 signals (4 counting the variable) in my process, and only those signals. If a signal is driven in one process, it shouldn't be driven anywhere else but that process. Not outside the process, not in another process. A signal is driven inside one process and one process only. You can compare the signal to other signals in other places (if statements, and such), but don't give the signal a value anywhere except in one process. And generally, it is defined in the reset portion, and then wherever necessary in the process proper. But only 1 process. If I'd been told this, it would have saved me tons of time while I was learning.
Here's the whole code in one chunk:
Vhdl Program For Parallel In Serial Out Shift Register
stanristanriParallel In Serial Out Block Diagram
@stanri's answer is impresively thorough and quite accurate... if I may summarize/clarify the first statement though, the 'for' statement in an HDL simply expresses 'syntactic replication' not 'sequential execution'.
That is to say, it simply generates more hardware elements (gates), and does not inform process flow. I would say the loop is expanded at elaboration time (compilation), not that it 'executes in zero time', after all at runtime there will still be propagation delay through the elements generated by the 'for' construct.
Don't start by writing VHDL code, start by drawing logic schematics (at least at some level of abstraction). At the end of the day HDL is just a text-based way of expressing the content of logic schematics.
Nick Alexeev♦protected by Community♦Apr 23 '15 at 14:30
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I'm creating an n bit shift register. When the enable signal is high, I want the shift register to shift n times, irrespective of whether enable continues to be high or low. I've put a for loop to shift n times inside a process. My code is given below.
I don't think the for loop is working, as the shifting is not restricted to n times. Where am I going wrong?
Federico Russo2 Answers
$begingroup$In VHDL, a for loop executes in zero time. This means that instead of waiting a clock cycle between each iteration, the entire loop is run within one clock cycle, with only the final result of the loop being shown at the end. This is what's happening in your code. The entire loop is executing in a single clock cycle, and the value of s_out is only going to change once - to the value it was when the loop ended, which in this case is s_in shifted by 4.
What you really want is a loop where each iteration occurs on a new clock edge. This allows for s_in to be shifted out of s_out ever clock cycle.
Performing a loop where each iteration occurs on a clock edge does not require a for loop command, instead it takes advantage of the sensitivity list of the process. Here's how:
A process is triggered every time one of the signals on the sensitivity list ('clk, reset' in this case) changes. This means that the process is already looping every clock cycle (if a clock is in the sensitivity list). You can use this to your advantage in order to perform a for-loop type operation, where every iteration of the loop occurs on a clock cycle.
First you need a counter:
shift_counter keeps track of how many iterations (or shifts) have occurred so far. you'll compare shift_counter to n-1 to see if you're done yet.
Next it might be a good idea to think of the states your process will be in. Perhaps a wait state for when the process is not shifting, and a shifting state for when it is.
The state signal definition:
In the process proper:
Ok, so what happens when we're waiting for an enable? It would be a good idea to set all (driven) variables to a known value. This means that maybe something like this is a good idea:
This is useful to do because then you know exactly what your signal values are when enable goes high. Also, at the end of the shift, you can change states back to 'waiting' in order to get ready for enable again.
So what is going to trigger a state change from waiting to shifting ?That's easy:
Ok, so next state. shifting.
First, we want to increment the shift counter, and perform the actual shift:
And then also detect when the shifting is done, in order to leave the shift state and go back to waiting:
And that's it!
In the below chunk of code, note that the 'reset' state and the 'waiting' state are distinct. This is useful because generally the asynchronous reset only occurs at startup and is not expected to process any data during this time. By moving the temp_reg <= parallel_in to the waiting state (outside of the asynchronous reset), we are allowing the module driving parallel_in to start up correctly without having to send data during reset. Also, now the waiting state can be entered as necessary, without having to perform an asynchronous reset.
Also notice that I'm only driving 3 signals (4 counting the variable) in my process, and only those signals. If a signal is driven in one process, it shouldn't be driven anywhere else but that process. Not outside the process, not in another process. A signal is driven inside one process and one process only. You can compare the signal to other signals in other places (if statements, and such), but don't give the signal a value anywhere except in one process. And generally, it is defined in the reset portion, and then wherever necessary in the process proper. But only 1 process. If I'd been told this, it would have saved me tons of time while I was learning.
Here's the whole code in one chunk:
stanristanri@stanri's answer is impresively thorough and quite accurate... if I may summarize/clarify the first statement though, the 'for' statement in an HDL simply expresses 'syntactic replication' not 'sequential execution'.
That is to say, it simply generates more hardware elements (gates), and does not inform process flow. I would say the loop is expanded at elaboration time (compilation), not that it 'executes in zero time', after all at runtime there will still be propagation delay through the elements generated by the 'for' construct.
Don't start by writing VHDL code, start by drawing logic schematics (at least at some level of abstraction). At the end of the day HDL is just a text-based way of expressing the content of logic schematics.
Nick Alexeev♦Shift Register
$endgroup$protected by Community♦Apr 23 '15 at 14:30
Thank you for your interest in this question. Because it has attracted low-quality or spam answers that had to be removed, posting an answer now requires 10 reputation on this site (the association bonus does not count).
Would you like to answer one of these unanswered questions instead?